BOGUS Szymon accepted merge request !10: Add AXI master for memory access at BOGUS Szymon / RISCV-Research-Project

BOGUS Szymon
2025-12-01T12:29:25Z

Adds a memory arbiter that coordinates between instruction fetching and load/stores, executing the requested operation via AXI4 Lite. In addition these changes are integrated by splitting the entire core into multiple stages that use the valid/ready handshake to handoff data between them. For simulation of the full CPU, the previous memories are replaced by a newly added AXI memory mock that acts as an AXI slave.

the testbench for the memory arbiter is still a WIP